1. Technical Field
The present invention relates to a semiconductor device, a lower layer wiring designing device, a method of designing lower layer wirings and a computer program.
2. Related Art
In recent years, MIM (Metal Insulator Metal) structures are applied not only to DRAMs (Dynamic Random Access Memory), but also to Decoupling Capacitors, in the field of LSI (Large Scale Integration). The MIM structure as an integrated module of LSI has become increasingly important. Thus, it has been common to mount the MIM structure in LSI.
However, the MIM capacitors may cause a failure of LSI having the MIM capacitors therein or a failure of the entire system due to an increase in leakage current resulting from the structural disruption. Therefore, desired is a technique for restraining an increase in a leakage current due to the MIM capacitors.
Such a technique is disclosed, for example, in Japanese Laid-open patent publication No. 2006-228977.
According to the technique disclosed in Japanese Laid-open patent publication No. 2006-228977, in a process of forming a copper wiring arranged underneath MIM capacitors, a trench formed in an interlayer insulating film is filled with copper to restrain an increase in a leakage current due to a Dishing phenomenon that occurs during CMP processing. More specifically, according to the technique, it is possible to restrain an increase in the leakage current due to a gap generated at the boundary between the copper wiring and the interlayer insulating layer caused by the Dishing phenomenon. Japanese Laid-open patent publication No. 2006-228977 discloses, a semiconductor device, in which an interlayer insulating film is formed on a copper diffusion prevention film formed on a layer composed of a copper wiring and an interlayer insulating film, and further the MIM capacitors are formed thereon. According to this configuration, the gap is absorbed by the interlayer insulating film, thereby realizing a decrease in the leakage current.
FIG. 9 shows a schematic cross-sectional view of a semiconductor device including MIM capacitors.
The semiconductor device shown in FIG. 9 has a lower layer wiring 110 including copper (Cu) or aluminum (Al) as a main compound underneath an MIM capacitor 200, which is composed of a lower electrode 210, a capacity dielectric film 220 and an upper electrode 230.
As shown, a hillock that is a projection having the same compound as that of the lower layer wiring 110 may be generated, from the grain boundary, in the lower layer wiring 110. The hillock may possibly be generated at the production. However, a wiring cap film 500 an interlayer insulating film 600, the lower electrode 210, the capacity dielectric film 220 and the upper electrode 230 formed on the lower layer wiring layer 100, are formed generally by sputtering or CVD. Thus, the projection form by the hillock cannot be absorbed. The projection form by the hillock is reflected to the film(s) formed above the lower layer wiring layer 100. Because the capacity dielectric film 220 is made thin, the film may be fissured as shown in the diagram due to reflection of the projection form by the hillock. This damage is affected by the process temperatures of the stress of the laminated interlayer film. The fissure of the capacity dielectric film 220 causes an increase in the leakage current.
Accordingly, the structural disruption of the MIM capacitors 20 occurs due to the hillock generated from the lower layer wiring 110, in the structure with the lower layer wiring 110 including Cu or Al as a main compound underneath the MIM capacitor 200. This results in an increase in the leakage current. Even in the structure of the semiconductor device disclosed in Japanese Laid-open patent publication No. 2006-228977, the projection form by the hillock is reflected to a film (s) such as he interlayer insulating film formed on the lower layer wiring 110. This may cause a fissure of the capacity dielectric film 220.